The driver is a network device driver of PF_CAN protocol family.

dev.c Operation about parameters
drv.c Network device driver
mbm.c Management of message buffer
flexcan.h Head file of FlexCAN

• br_clksrc configures the clock source
• bitrate configures the bitrate. Currenlty, this parameter only shows the bitrate that is supported.
To ensure bitrate exactly, set the individual parameters:
— br_presdiv configures prescale divider
— br_rjw configures RJW
— br_propseg configures the length of the propagation segment
— br_pseg1 configures the length of phase buffer segment 1
— br_pseg2 configures the length of phase buffer segment 2
• abort enables or disables abort feature
• bcc sets backwards compatibility with previous FlexCAN versions
• boff_rec configures support of recover from bus off state
• fifo enables or disables FIFO work mode
• listen enables or disables listen only mode
• local_priority enables or disables the local priority. In current version, this parameter is not used
• loopback sets hardware at loopback mode or not
• maxmb sets the maximum message buffers
• smp sets the sampling mode
• srx_dis disables or enables the self-reception
• state shows the device status
• ext_msg configures support for extended message
• std_msg configures support for standard message
• tsyn enables or disables timer synchronization feature
• wak_src sets wakeup source
• wakeup enables or disables self-wakeup
• xmit_maxmb sets the maximum message buffer for the transmission

The module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts due to ORed interrupts from message buffers, bus-off, error, Tx warning, Rx warning, and wake-up).
message buffer (MB)

The FlexCAN includes the following submodules:
• An embedded RAM for storing message buffers (64 message buffers are supported)
• An embedded RAM for storing individual Rx mask registers
• A CAN protocol interface (CPI) submodule that manages the serial communication on the CAN
bus: requesting RAM access for receiving and transmitting message frames, validating received
messages and performing error handling.
• A message buffer management (MBM) submodule which handles message buffer selection for
reception and transmission, taking care of arbitration and ID-matching algorithms.
• A bus interface unit (BIU) submodule which controls the access to and from the internal interface
bus, in order to establish connection to the ARM and to other blocks. Clocks, address and data
buses, interrupt outputs, and test signals are accessed through the bus interface unit.

Simultaneous reception through FIFO and mailbox is supported.